1. Field of the Invention
The present invention relates to a semiconductor integrated circuit employing a smaller number of elements to provide a phase-locked clock signal.
2. Description of the Related Art
Recent memory devices operate at a high speed of, for example, over 100 MHz, and therefore, employ a DLL (delay locked line) circuit to lock the phase of an internal clock signal with respect to the phase of an external clock signal, thereby suppressing an access delay or an access fluctuation in a real internal clock signal line.
The DLL circuit employs a dummy line for transmitting a dummy internal clock signal and estimates a propagation delay due to load on the real internal clock signal line.
Namely, a high-speed, highly-integrated semiconductor circuit needs a phase-locked clock signal. For example, a synchronized DRAM (SDRAM) must provide a phase-locked clock signal to output buffers. The phase-locked clock signal is generated by a delay-locked line (DLL) circuit having delay gates and control circuits that occupy a large area.
The prior arts and their associated problems will be described in detail later with reference to the accompanying drawings.